Serial interfaces are widely employed for the exchange of digital data between electronic circuits and devices. Some advantages of the serial interface include low pin and wire count for the interconnection medium, low susceptibility to electromagnetic interference (EMI), and low power consumption. A popular application for a serial digital interface (SDI) is the connection of a host computer or processor with an imaging device, a display device such as a Liquid Crystal Display (LCD), or a camera. The SDI provides a means for data exchange between the devices, enabling, for example, the transfer of an image from a camera to a personal computer for sharing, archiving, or modification.
Before data can be shared across a serial link, the data must be formatted into a configuration which matches the particular protocol specifications for the link, and then passed to a serializer modulator circuit. The serializer modulator accepts data in discrete units, typically bytes or words, and translates the data into a series of bits which are conveyed sequentially across the interconnection medium. At the receiving end of the medium, a deserializer demodulator accepts the series of bits and recombines them to recreate the original sequence of data units. The action of the serializer modulator is typically placed under control of a system clock, which determines the rate at which data units are converted by the serializer into a bit sequence and subsequently sent over the interconnection medium. Similarly, the deserializer demodulator accepts the bit sequence at the rate sent by the serializer modulator, and passes the recreated data to the system at a rate controlled by a synchronization clock. In some cases, a clock signal is sent as part of the serial data conveyed by the interface, either embedded within the serialized data, or by means of a separate line dedicated to the clock signal.
The construction of serializer/deserializer (SERDES) circuits is well known in the art. The usual method of interfacing an electronic circuit to the modulator and demodulator circuits within the SERDES is to provide separate interface circuits for a transmit interface and a receive interface. These separate interface circuits each usually communicate with the modulator and demodulator circuits by means of a parallel bus. Furthermore, the interface circuits are typically specific to an intended application. That is, an interface circuit may be designed to convey only 8-bit data or only 16-bit data. In addition, the circuits are usually configured to accommodate a single mode of operation. For example, if the interface is designed to send a clock signal in addition to the data, the circuit cannot be operated without the included clock signal.
It is generally desirable to maximize the performance of a serial interface in terms of bit rate, power consumption, or other performance attributes. One method of achieving this objective is to reduce the number of bits which must be sent over the interface by employing data compression. Often times, data compression is accomplished by software means or by dedicated circuitry to implement a compression algorithm.
What is needed, therefore, is an apparatus and method for interfacing a host circuit to a parallel bus which extends the art by providing both transmit and receive capability, configuration flexibility, and data compression within a single circuit. Additionally, incorporation of data compression enables the possibility of using Return-To-Zero (RTZ) or Return-To-One (RTO) formats for the serial data. This, in turn, opens up a wider range of transmission techniques including Pulse Width Modulation (PWM) and derivatives thereof. In this manner, the usefulness of serial interfaces is enhanced. It will also be appreciated by those skilled in the art that such a capability has other application to data transfer both within and between electronic circuits and devices for example, providing a method of increasing an effective bandwidth of an on-chip parallel bus, while increasing the flexibility and options for interfacing circuit blocks to the parallel bus.